1. Field of the Invention
This invention relates to computer memory addressing, and particularly to a burst address sequence generator for producing a sequence of memory addresses that are compatible with a memory burst cycle of a microprocessor.
2. Description of the Prior Art
The pulse train burst address sequence of a central processing unit (CPU) of the INTEL 80486 is determined by the starting address. The customary technique involves using a clocked state machine to determine the burst address sequence based on the value of the starting address. To generate 2.sup.n pulse train addresses, at least (2.sup.n)+1 states and n outputs are required. If the state machine is implemented in the form of a programmable array logic (PAL) or a programmable logic device (PLD), then (n+1)+n register outputs are required to hold the (2.sup.n)+1, states in the state machine and the n bits of pulse train addresses.
When n=2, the four pulse train burst cycles will require at least 2+1+2=5 register outputs. Or, when n=3 (as in the case of write back cache of the INTEL apogee module), the eight pulse train burst cycles will require at least 3+1+3=7 register outputs. In this situation, there are generally only eight signals that need be input to the state machine, so a single
or PLD (with 20 or 24 pins) can accomplish the task.
When n=4 (not currently used in INTEL microprocessors), however, system design may make it possible to divide a 128-bit pulse train into two 64-bit pulse trains. Thus, eight 128-bit pulse train burst cycles will become 16 pulse train burst cycles. This would require a minimum of 4+1+4=9 register outputs. In this case, the design can only be completed by adding an additional PAL or PLD.
In conclusion, for each increment of 1 in n, the required number of register outputs must be increased by at least two. With this approach, the following problems will exist: (1) the number of required PALs or PLDs must be increased as n increases; (2) because this method of implementation is not easily expandable, the state machine must be completely redesigned as n increases; (3) debugging of the new state machine design must be repeated for every increase in n.
An object of the present invention is to provide a pulse train address sequence generator which can be randomly expanded. Another object of the present invention is to provide a pulse train address sequence generator that has the following functions and effects.
1. The generator can be produced at low cost using conventional transistor- transistor logic (TTL) elements. PA1 2. The circuitry is simple and reliable. PA1 3. Expansion can be randomly carried out to support 2.sup.n pulse train sequences. PA1 4. Expansion can be effected by repeatedly using the identical elements without redesigning the circuit or debugging.